ADC 6021 Spécifications télécharger pdf (Page 25)

MYXPM6021*

Revision 1.1 - 10/21/14

*Advanced information. Subject to change without notice.

MYXPM6021*

Form #: CSI-D-685 Document 011

8.2.1 Sequencing

EachPMICcomponent(suchasaDC/DCconverter,LDO,internalorexternalpowerswitch…)canbeconguredwith

greatexibilitytocontrolthepowersequencing,includingtheindependentenablinganddisablingofeachcomponent

duringpower-upandpower-down.ThesequencingisdenedbytheIntelprocessorspecication,withtheimplementation

accordingly.Customersrequestingpowersequencingotherthanspecied,shouldcontactMicrossComponents.

8.3 MYXPM6021 Power Sequences

Thereare10powerstatetransitionssupportedbytheMYXPM6021.Theseare:

• ColdBoot:Acoldbootsequencebeginsatthe“SOCG3”state,andterminatesatthe“SOCS0”state.Onceallof

therailsareon,theCOREPWROKsignalwillassertandthePLTRST_Bwillde-assert.Thiswilleffectivelyturnonthe

SOCinorderforittobeginexecutingcodeandcontrollingthesystem.

• WarmReset:AWarmResetresetstheSOCaswellastheI2CandSVIDinterfaces(resetcorrespondingstate

machine,ignoreanyon-goingtransactiononthebus)inthePMIC.InadditiontheVCC,VNNwillchangetheoutput

voltagetotheVBOOTsettings.PMICcongurationregistersarenotresettodefault.DuringaWarmReset,onlythe

PLTRST_BpintotheSOCistoggled.Allrailsremaininregulation.WarmresetcanonlybeissuedwhiletheSoCstays

inSOC_S0state.

• EnterSOCS0iX:TheS0IXstateisenteredwhentheSOCisinashallowsleepstate.Thisstateisenteredwhenthe

SOCassertstheSLP_S0IX_B(LOW)pintothePMIC.VDDQ_VTTandSXrailsareturnedoff.TheVCCrailisturned

offbySVIDcommands(notbySLP_S0IX_Bsignal).TherestoftheVRsremainonbutenterintopowersavemode.

• ExitSOCS0iX:TheS0IXstateisexitedwhentheSOCde-assertstheSLP_S0IX_Bpin(HIGH).VDDQ_VTTand

SXrailsareturnedon.TheVCCrailwillbeturnedonbySVIDcommands(notbySLP_S0IX).Therestoftherailswill

comeoutofpowersavemode.ExitingtheSOC_SXstatewillbeperformedwithinmaximum200μs.

• EnterSOC_S3:TheS3stateisenteredwhentheSOCassertstheSLP_S3_Bpin(LOW).VRsthatremainonenter

intopowersavemode.

• ExitSOC_S3:TheS3stateisexitedwhentheSOCde-assertstheSLP_S3_Bpin(HIGH).Voltagerailswillbe

turnedonandcomeoutofpowersavemode.ExitingSOC_S3statewillbeperformedwithin2msmaximum.

• EnterSOC_S4:TheS4stateisenteredwhentheSOCassertstheSLP_S4_Bpin(LOW).VRsthatremainonenter

intopowersavemode.

• ExitSOC_S4:TheS4stateisexitedwhentheSOCde-assertstheSLP_S4_Bpin(HIGH).Voltagerailswillbe

turnedonandcomeoutofpowersavemode.

• ColdOFF:PMICwillgointoSOC_G3andstayuntilawakeupeventisnotbringingitbacktoactivestate.

• ModemReset:AModemResettaskisinitiatedbysettingtheMODEMRSTSEQbitintheMODEMCTRLregister.

(TheMODEMOFFbitinthesameregisterdirectlycontrolsthestatusoftheMODEM_OFF_Boutputpin,butdoesnot

launchthistask).TheModemResettasktogglestheSDWNandMODEM_OFF_Bpins,implementingappropriate

(modem-specic)delaytimings.

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