ADC 6 Spécifications télécharger pdf (Page 61)

CLK

Master

ADC12D1XXX

Slave 1

ADC12D1XXX

Slave 2

ADC12D1XXX

CLK

RCLK

RCOut1

RCOut2

DCLK

DCLK DCLK

RCLK

RCOut1

RCOut2

RCOut1

RCOut2

ADC12D1800RF

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SNAS518I –JULY 2011–REVISED JANUARY 2014

Figure 6-9. AutoSync Example

In order to synchronize the DCLK (and Data) outputs of multiple ADCs, the DCLKs must transition at the

same time, as well as be in phase with one another. The DCLK at each ADC is generated from the CLK

after some latency, plus t

minus t

. Therefore, in order for the DCLKs to transition at the same time,

the CLK signal must reach each ADC at the same time. To tune out any differences in the CLK path to

each ADC, the t

adjust feature may be used. However, using the t

adjust feature will also affect when

the DCLK is produced at the output. If the device is in Demux Mode, then there are four possible phases

which each DCLK may be generated on because the typical CLK = 1.8 GHz and DCLK = 450 MHz for this

case. The RCLK signal controls the phase of the DCLK, so that each Slave DCLK is on the same phase

as the Master DCLK.

The AutoSync feature may only be used via the Control Registers. For more information, see AN-2132 .

6.4.4.2 DCLK Reset Feature

The DCLK reset feature is available via ECM, but it is disabled by default. DCLKI and DCLKQ are always

synchronized, by design, and do not require a pulse from DCLK_RST to become synchronized.

The DCLK_RST signal must observe certain timing requirements, which are shown in Figure 4-7 of the

Timing Diagrams. The DCLK_RST pulse must be of a minimum width and its deassertion edge must

observe setup and hold times with respect to the CLK input rising edge. These timing specifications are

listed as t

PWR

, t

and t

and may be found in Converter Electrical Characteristics AC Electrical

Characteristics.

The DCLK_RST signal can be asserted asynchronously to the input clock. If DCLK_RST is asserted, the

DCLK output is held in a designated state (logic-high) in Demux Mode; in Non-Demux Mode, the DCLK

continues to function normally. Depending upon when the DCLK_RST signal is asserted, there may be a

narrow pulse on the DCLK line during this reset event. When the DCLK_RST signal is de-asserted, there

are t

SYNC_DLY

CLK cycles of systematic delay and the next CLK rising edge synchronizes the DCLK output

with those of other ADC12D1800RFs in the system. For 90° Mode (DDRPh = logic-high), the

synchronizing edge occurs on the rising edge of CLK, 4 cycles after the first rising edge of CLK after

DCLK_RST is released. For 0° Mode (DDRPh = logic-low), this is 5 cycles instead. The DCLK output is

enabled again after a constant delay of t

For both Demux and Non-Demux Modes, there is some uncertainty about how DCLK comes out of the

reset state for the first DCLK_RST pulse. For the second (and subsequent) DCLK_RST pulses, the DCLK

will come out of the reset state in a known way. Therefore, if using the DCLK Reset feature, it is

recommended to apply one "dummy" DCLK_RST pulse before using the second DCLK_RST pulse to

synchronize the outputs. This recommendation applies each time the device or channel is powered-on.

When using DCLK_RST to synchronize multiple ADC12D1800RFs, it is required that the Select Phase

bits in the Control Register (Addr: Eh, Bits 3,4) be the same for each Master ADC12D1800RF.

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