ADC 6 Spécifications télécharger pdf (Page 47)

ADC12D1800RF

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SNAS518I –JULY 2011–REVISED JANUARY 2014

Table 6-4. Features and Modes (continued)

Control Pin

Feature Non-ECM ECM Default ECM State

Active in ECM

LVDS Differential Voltage Selected via the OVS Bit

Higher amplitude only N/A Higher amplitude

Amplitude Selection (Addr: 0h; Bit: 13)

LVDS Common-Mode Voltage Selected via V

Yes Not available N/A

Amplitude Selection

(1)

(Pin B1)

Output Formatting Selection Selected via the 2SC Bit

Offset Binary only N/A Offset Binary

(1)

(Addr: 0h; Bit: 4)

Selected via TPM Selected via the TPM Bit

Test Pattern Mode at Output No TPM disabled

(Pin A4) (Addr: 0h; Bit: 12)

Demux/Non-Demux Mode Selected via NDM

Yes Not available N/A

Selection (Pin A5)

Selected via the Config Reg Master Mode,

AutoSync Not available N/A

(Addr: Eh) RCOut1/2 disabled

Selected via the Config Reg

DCLK Reset Not available N/A DCLK Reset disabled

(Addr: Eh; Bit 0)

Selected via the TSE Bit

Time Stamp Not available N/A Time Stamp disabled

(Addr: 0h; Bit: 3)

Calibration

Selected via CAL Selected via the CAL Bit N/A

On-command Calibration Yes

(Pin D6) (Addr: 0h; Bit: 15) (CAL = 0)

Power-on Calibration Delay Selected via CalDly

Yes Not available N/A

Selection

(3)

(Pin V4)

Selected via the Config Reg

Calibration Adjust

(3)

Not available N/A t

CAL

(Addr: 4h)

Read / Write Calibration Selected via the SSC Bit R/W calibration values

Not available N/A

Settings

(3)

(Addr: 4h; Bit: 7) disabled

Power-Down

Selected via PDI Selected via the PDI Bit

Power down I-channel Yes I-channel operational

(Pin U3) (Addr: 0h; Bit: 11)

Selected via PDQ Selected via the PDQ Bit

Power down Q-channel Yes Q-channel operational

(Pin V3) (Addr: 0h; Bit: 10)

(3) The -3 dB point is the traditional Full-Power Bandwidth (FPBW) specification. Although the insertion loss is approximately half the power

at this frequency, the dynamic performance of the ADC does not necessarily begin to degrade to a level below which it may be

effectively used in an application. The ADC may be used at input frequencies above the -3 dB FPBW point, for example, into the 3rd

Nyquist zone. Depending on system requirements, it is only necessary to compensate for the insertion loss.

6.3.1 Input Control and Adjust

There are several features and configurations for the input of the ADC12D1800RF so that it may be used

in many different applications. This section covers AC/DC-coupled Mode, input full-scale range adjust,

input offset adjust, DES/Non-DES Mode, DES Timing Adjust, and sampling clock phase adjust.

6.3.1.1 AC/DC-coupled Mode

The analog inputs may be AC or DC-coupled. See AC / DC-Coupled Mode Pin (VCMO) for information on

how to select the desired mode and DC-coupled Input Signals and AC-coupled Input Signals for

applications information.

6.3.1.2 Input Full-Scale Range Adjust

The input full-scale range for the ADC12D1800RF may be adjusted in ECM. In Non-ECM, the control pin

must be set to logic-high; see Full-Scale Input Range Pin (FSR). In ECM, the input full-scale range may

be adjusted with 15-bits of precision. See V

IN_FSR

in Converter Electrical Characteristics Analog Input /

Output and Reference Characteristics for electrical specification details. Note that the full-scale input

range setting in Non-ECM (logic-high only) corresponds to the lowest full-scale input range settings in

ECM. It is necessary to execute an on-command calibration following a change of the input full-scale

range. See Register Definitions for information about the registers.

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