Data
DCLK
SDR Rising
DCLK
SDR Falling
ADC12D1800RF
SNAS518I –JULY 2011–REVISED JANUARY 2014
www.ti.com
For SDR, the DCLK frequency is the same as the data rate and data is sent to the outputs on a single
edge of DCLK; see Figure 6-4. The Data may transition on either rising or falling edge of DCLK. Any offset
from this timing is t
OSK
; see Converter Electrical Characteristics AC Electrical Characteristics for details.
The DCLK rising / falling edge may be selected via the SDR bit in the Configuration Register (Addr: 0h;
Bit: 2) in ECM only. Note that SDR is available in Demux Mode, but not in Non-Demux Mode.
Figure 6-4. SDR DCLK-to-Data Phase Relationship
6.3.2.2 LVDS Output Differential Voltage
The ADC12D1800RF is available with a selectable higher or lower LVDS output differential voltage. This
parameter is V
OD
and may be found in Converter Electrical Characteristics Digital Control and Output Pin
Characteristics. The desired voltage may be selected via the OVS Bit (Addr: 0h, Bit 13). For many
applications, in which the LVDS outputs are very close to an FPGA on the same board, for example, the
lower setting is sufficient for good performance; this will also reduce the possibility for EMI from the LVDS
outputs to other signals on the board. See Register Definitions for more information.
6.3.2.3 LVDS Output Common-Mode Voltage
The ADC12D1800RF is available with a selectable higher or lower LVDS output common-mode voltage.
This parameter is V
OS
and may be found in Converter Electrical Characteristics Digital Control and Output
Pin Characteristics. See LVDS Output Common-mode Pin (VBG) for information on how to select the
desired voltage.
6.3.2.4 Output Formatting
The formatting at the digital data outputs may be either offset binary or two's complement. The default
formatting is offset binary, but two's complement may be selected via the 2SC Bit (Addr: 0h, Bit 4); see
Register Definitions for more information.
6.3.2.5 Demux/Non-demux Mode
The ADC12D1800RF may be in one of two demultiplex modes: Demux Mode or Non-Demux Mode (also
sometimes referred to as 1:1 Demux Mode). In Non-Demux Mode, the data from the input is simply output
at the sampling rate on one 12-bit bus. In Demux Mode, the data from the input is output at half the
sampling rate, on twice the number of buses. Demux/Non-Demux Mode may only be selected by the NDM
pin; see Non-Demultiplexed Mode Pin (NDM). In Non-DES Mode, the output data from each channel may
be demultiplexed by a factor of 1:2 (1:2 Demux Non-DES Mode) or not demultiplexed (Non-Demux Non-
DES Mode). In DES Mode, the output data from both channels interleaved may be demultiplexed (1:4
Demux DES Mode) or not demultiplexed (Non-Demux DES Mode).
Note that for Non-Demux Mode, 90° DDR Mode and SDR Mode are not available. See Table 6-5 for a
selection of available modes.
50 Functional Description Copyright © 2011–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: ADC12D1800RF
(33 pages)
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Commentaires sur ces manuels