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ADC12D1800RF

SNAS518I –JULY 2011–REVISED JANUARY 2014

www.ti.com

3.10 Converter Electrical Characteristics

Digital Control and Output Pin Characteristics

ADC12D1800RF

Units

Symbol Parameter Conditions

(Limits)

Typ Lim

Digital Control Pins (DES, CalDly, CAL, PDI, PDQ, TPM, NDM, FSR, DDRPh, ECE, SCLK, SDI, SCS)

Logic High Input Voltage 0.7×V

V (min)

Logic Low Input Voltage 0.3×V

V (max)

Input Leakage Current;

0.02 μA

= V

Input Leakage Current; FSR, CalDly, CAL, NDM, TPM,

-0.02 μA

= GND DDRPh, DES

SCS, SCLK, SDI -17 μA

PDI, PDQ, ECE -38 μA

IN_DIG

Digital Control Pin Input Measured from each control pin to

1.5 pF

Capacitance

(1)

GND

Digital Output Pins (Data, DCLKI, DCLKQ, ORI, ORQ)

LVDS Differential Output Voltage V

= Floating, OVS = High mV

P-P

400

(min)

630

P-P

800

(max)

= Floating, OVS = Low mV

P-P

230

(min)

460

P-P

630

(max)

= V

, OVS = High 670 mV

P-P

= V

, OVS = Low 500 mV

P-P

ΔV

O DIFF

Change in LVDS Output Swing

±1 mV

Between Logic Levels

Output Offset Voltage

(2)

= Floating 0.8 V

= V

1.2 V

ΔV

Output Offset Voltage Change See

(1)

±1 mV

Between Logic Levels

Output Short Circuit Current

(2)

= Floating;

±4 mA

D+ and D− connected to 0.8V

Differential Output Impedance See

(2)

100 Ω

Logic High Output Level CalRun, I

= −100 µA,

(2)

1.65 V

SDO, I

= −400 µA

(2)

Logic Low Output Level CalRun, I

= 100 µA,

(2)

0.15 V

SDO, I

= 400 µA

(2)

Differential DCLK Reset Pins (DCLK_RST)

CMI_DRST

DCLK_RST Common Mode Input See

(2)

1.25 V

Voltage

ID_DRST

Differential DCLK_RST Input See

(2)

IN_CLK

P-P

Voltage

IN_DRST

Differential DCLK_RST Input See

(2)

100 Ω

Resistance

(1) This parameter is specified by design and is not tested in production.

(2) This parameter is specified by design and/or characterization and is not tested in production.

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