ADC 6 Spécifications Page 18

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V
DR
DR GND
+
-
+
-
V
DR
DR GND
+
-
+
-
ADC12D1800RF
SNAS518I JULY 2011REVISED JANUARY 2014
www.ti.com
Table 2-4. High-Speed Digital Outputs (continued)
Ball No. Name Equivalent Circuit Description
J18/J19 DI11+/-
H19/H20 DI10+/-
H17/H18 DI9+/-
G19/G20 DI8+/-
G17/G18 DI7+/-
F18/F19 DI6+/-
E19/E20 DI5+/-
I- and Q-channel Digital Data Outputs. In Non-
D19/D20 DI4+/-
Demux Mode, this LVDS data is transmitted at the
D18/E18 DI3+/-
sampling clock rate. In Demux Mode, these
C19/C20 DI2+/-
outputs provide ½ the data at ½ the sampling
B19/B20 DI1+/-
clock rate, synchronized with the delayed data, i.e.
B18/C17 DI0+/-
the other ½ of the data which was sampled one
· ·
clock cycle earlier. Compared with the DId and
M18/M19 DQ11+/-
DQd outputs, these outputs represent the later
N19/N20 DQ10+/-
time samples. If used, each of these outputs
N17/N18 DQ9+/-
should always be terminated with a 100Ω
P19/P20 DQ8+/-
differential resistor placed as closely as possible
P17/P18 DQ7+/-
to the differential receiver.
R18/R19 DQ6+/-
T19/T20 DQ5+/-
U19/U20 DQ4+/-
U18/T18 DQ3+/-
V19/V20 DQ2+/-
W19/W20 DQ1+/-
W18/V17 DQ0+/-
A18/A19 DId11+/-
B17/C16 DId10+/-
A16/B16 DId9+/-
B15/C15 DId8+/-
C14/D14 DId7+/-
A14/B14 DId6+/-
B13/C13 DId5+/-
C12/D12 DId4+/- Delayed I- and Q-channel Digital Data Outputs. In
A12/B12 DId3+/- Non-Demux Mode, these outputs are at TRI-
B11/C11 DId2+/- STATE. In Demux Mode, these outputs provide ½
C10/D10 DId1+/- the data at ½ the sampling clock rate,
A10/B10 DId0+/- synchronized with the non-delayed data, i.e. the
· · other ½ of the data which was sampled one clock
Y18/Y19 DQd11+/- cycle later. Compared with the DI and DQ outputs,
W17/V16 DQd10+/- these outputs represent the earlier time samples.
Y16/W16 DQd9+/- If used, each of these outputs should always be
W15/V15 DQd8+/- terminated with a 100Ω differential resistor placed
V14/U14 DQd7+/- as closely as possible to the differential receiver.
Y14/W14 DQd6+/-
W13/V13 DQd5+/-
V12/U12 DQd4+/-
Y12/W12 DQd3+/-
W11/V11 DQd2+/-
V10/U10 DQd1+/-
Y10/W10 DQd0+/-
18 Device Information Copyright © 2011–2014, Texas Instruments Incorporated
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