ADC UD-50 Spécifications

Quad, 14-Bit, 50 MSPSSerial LVDS 1.8 V ADCData Sheet AD9259 Rev. E Information furnished by Analog Devices is believed to be accurate and reliable.

AD9259 Data Sheet Rev. E | Page 10 of 52 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Rating ELECTRICAL AVDD to AGND −0.3 V to +2.0 V DRVDD to DR

Data Sheet AD9259 Rev. E | Page 11 of 52 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VIN + AVIN – AAVDDVIN + DVIN – DDRVDDNOTES1. THE EXPOSED THERM

AD9259 Data Sheet Rev. E | Page 12 of 52 Pin No. Mnemonic Description 30 CSB Chip Select Bar 31 PDWN Power-Down 33 VIN + A ADC A Analog Input

Data Sheet AD9259 Rev. E | Page 13 of 52 EQUIVALENT CIRCUITS VIN ± x05965-030 Figure 6. Equivalent Analog Input Circuit 10Ω10kΩ10kΩCLK–10Ω1.25VCLK+0

AD9259 Data Sheet Rev. E | Page 14 of 52 CSB70kΩ1kΩAVDD05965-034 Figure 12. Equivalent CSB Input Circuit SENSE1kΩ05965-036 Figure 13. Equivalent SEN

Data Sheet AD9259 Rev. E | Page 15 of 52 TYPICAL PERFORMANCE CHARACTERISTICS 0 105 15 20 250–120–80–100–60–20–40AMPLITUDE (dBFS)FREQUENCY (MHz)AIN =

AD9259 Data Sheet Rev. E | Page 16 of 52 10 252015 3530 4540 5090607065758580SNR/SFDR (dB)ENCODE (MSPS)2V p-p, SNR2V p-p, SFDR05965-059 Figure 21. S

Data Sheet AD9259 Rev. E | Page 17 of 52 SNR/SFDR (dB)5055606570758085901 10 100 1000ANALOG INPUT FREQUENCY (MHz)2V p-p, SFDR (dBc)2V p-p, SNR (dB)0

AD9259 Data Sheet Rev. E | Page 18 of 52 AMPLITUDE (dBFS)–1200–20–40–60–80–1000 5 10 15 20 25FREQUENCY (MHz)NPR = 63.89dBNOTCH = 18.0MHzNOTCH WIDTH

Data Sheet AD9259 Rev. E | Page 19 of 52 THEORY OF OPERATION The AD9259 architecture consists of a pipelined ADC divided into three sections: a 4-bi

AD9259 Data Sheet Rev. E | Page 2 of 52 TABLE OF CONTENTS Features ...

AD9259 Data Sheet Rev. E | Page 20 of 52 For best dynamic performance, the source impedances driving VIN + x and VIN − x should be matched such that

Data Sheet AD9259 Rev. E | Page 21 of 52 CLOCK INPUT CONSIDERATIONS For optimum performance, the AD9259 sample clock inputs (CLK+ and CLK−) should b

AD9259 Data Sheet Rev. E | Page 22 of 52 Clock Jitter Considerations High speed, high resolution ADCs are sensitive to the quality of the clock inpu

Data Sheet AD9259 Rev. E | Page 23 of 52 By asserting the PDWN pin high, the AD9259 is placed into power-down mode. In this state, the ADC typically

AD9259 Data Sheet Rev. E | Page 24 of 52 100500–100ps 0ps 100psTIE JITTER HISTOGRAM (Hits)500–5000–1.0ns –0.5ns 0ns 0.5ns 1.0nsEYE DIAGRAM VOLTAGE (

Data Sheet AD9259 Rev. E | Page 25 of 52 Two output clocks are provided to assist in capturing data from the AD9259. The DCO is used to clock the ou

AD9259 Data Sheet Rev. E | Page 26 of 52 When the SPI is used, the DCO phase can be adjusted in 60° increments relative to the data edge. This enabl

Data Sheet AD9259 Rev. E | Page 27 of 52 SCLK/DTP Pin The SCLK/DTP pin is for use in applications that do not require SPI mode operation. This pin c

AD9259 Data Sheet Rev. E | Page 28 of 52 Internal Reference Operation A comparator within the AD9259 detects the potential at the SENSE pin and conf

Data Sheet AD9259 Rev. E | Page 29 of 52 SERIAL PORT INTERFACE (SPI) The AD9259 serial port interface allows the user to configure the converter for

Data Sheet AD9259 Rev. E | Page 3 of 52 REVISION HISTORY 12/11—Rev. D to Rev. E Changes to Output Signals Section and Figure 60 ...

AD9259 Data Sheet Rev. E | Page 30 of 52 05965-093NUMBER OF SDIO PINS CONNECTED TOGETHERVOH (V)1.7151.7201.7251.7301.7351.7401.7451.7501.7551.7601.76

Data Sheet AD9259 Rev. E | Page 31 of 52 MEMORY MAP READING THE MEMORY MAP TABLE Each row in the memory map register table (Table 16) has eight addr

AD9259 Data Sheet Rev. E | Page 32 of 52 Table 16. Memory Map Register Addr. (Hex) Register Name (MSB) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit

Data Sheet AD9259 Rev. E | Page 33 of 52 Addr. (Hex) Register Name (MSB) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) Bit 0 Default Value

AD9259 Data Sheet Rev. E | Page 34 of 52 Power and Ground Recommendations When connecting power to the AD9259, it is recommended that two separate 1

Data Sheet AD9259 Rev. E | Page 35 of 52 EVALUATION BOARD The AD9259 evaluation board provides all of the support cir-cuitry required to operate the

AD9259 Data Sheet Rev. E | Page 36 of 52 DEFAULT OPERATION AND JUMPER SELECTION SETTINGS The following is a list of the default and optional settings

Data Sheet AD9259 Rev. E | Page 37 of 52 ALTERNATIVE ANALOG INPUT DRIVE CONFIGURATION The following is a brief description of the alternative analog

AD9259 Data Sheet Rev. E | Page 38 of 52 CHANNEL AP101AINAINVGA INPUT CONNECTIONVGA INPUT CONNECTIONVGA INPUT CONNECTIONVGA INPUT CONNECTION123654T1

Data Sheet AD9259 Rev. E | Page 39 of 52 CSBC2170.1µFC2200.1µFC2210.1µFC2180.1µFC2190.1µFC2230.1µFC2220.1µFAVDD_3.3VCLKCLKBGNDGND_PADOUT0OUT0BOUT1OUT

AD9259 Data Sheet Rev. E | Page 4 of 52 SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5

AD9259 Data Sheet Rev. E | Page 40 of 52 CWPOWER DOWN ENABLE(0V TO 1V = DISABLE POWER)EXTERNAL VARIABLE GAIN DRIVEVARIABLE GAIN CIRCUIT(0V TO 1.0V D

Data Sheet AD9259 Rev. E | Page 41 of 52 MODE PINPOSITIVE GAIN SLOPE = 0V TO 1.0VNEGATIVE GAIN SLOPE = 2.25V-5.0VHILO PINHI GAIN RANGE = 2.25V-5.0VL

AD9259 Data Sheet Rev. E | Page 42 of 52 MOUNTING HOLESCONNECTED TO GROUNDH2H3H1H4P1P2P3P4P5P6P7P8OPTIONAL POWER INPUT+5.0V+1.8V+1.8V+3.3V12345678P5

Data Sheet AD9259 Rev. E | Page 43 of 52 05965-020 Figure 67. Evaluation Board Layout, Primary Side

AD9259 Data Sheet Rev. E | Page 44 of 52 05965-021 Figure 68. Evaluation Board Layout, Ground Plane

Data Sheet AD9259 Rev. E | Page 45 of 52 05965-022 Figure 69. Evaluation Board Layout, Power Plane

AD9259 Data Sheet Rev. E | Page 46 of 52 05965-023 Figure 70. Evaluation Board Layout, Secondary Side (Mirrored Image)

Data Sheet AD9259 Rev. E | Page 47 of 52 Table 17. Evaluation Board Bill of Materials (BOM)1 Item Qty. Reference Designator Device Package Valu

AD9259 Data Sheet Rev. E | Page 48 of 52 Item Qty. Reference Designator Device Package Value Manufacturer Manufacturer’s Part Number 17 1 F

Data Sheet AD9259 Rev. E | Page 49 of 52 Item Qty. Reference Designator Device Package Value Manufacturer Manufacturer’s Part Number 35 15

Data Sheet AD9259 Rev. E | Page 5 of 52 AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −

AD9259 Data Sheet Rev. E | Page 50 of 52 Item Qty. Reference Designator Device Package Value Manufacturer Manufacturer’s Part Number 57 2 U

Data Sheet AD9259 Rev. E | Page 51 of 52 OUTLINE DIMENSIONS *COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2WITH EXCEPTION TO EXPOSED PAD DIMENSION.FORPR

AD9259 Data Sheet Rev. E | Page 52 of 52 NOTES ©2006–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the

AD9259 Data Sheet Rev. E | Page 6 of 52 DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AI

Data Sheet AD9259 Rev. E | Page 7 of 52 SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference,

AD9259 Data Sheet Rev. E | Page 8 of 52 TIMING DIAGRAMS DCO–DCO+D – xD + xFCO–FCO+VIN ± xCLK–CLK+MSBN – 9D12N – 9D11N – 9D10N – 9D9N – 9D8N – 9D7N –

Data Sheet AD9259 Rev. E | Page 9 of 52 05965-041DCO–DCO+D – xD + xFCO–FCO+VIN ± xCLK–CLK+LSBN – 9D0N – 9D1N – 9D2N – 9D3N – 9D4N – 9D5N – 9D6N – 9D7