ADC 6 Spécifications

ADC12D1800RFADC12D1800RF 12-Bit, Single 3.6 GSPS RF Sampling ADCData ManualPRODUCTION DATA information is current as of publication date.Products conf

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20AGND V_A SDO TPM NDM V_A GND V_E GND_E DId0+ V_DR DId3+ GND_DR DId6+ V_DR DId9+ GND_DR DId11+ DId11-

VAAGNDVAAGND100VAAGNDVAAGND100VBIAS50k50k50kVAAGNDVAAGND50kControl from VCMOVCMO100ADC12D1800RFwww.ti.comSNAS518I –JULY 2011–REVISED JANUARY 20142.4 B

VAVAGNDGNDTdiode_PTdiode_NGNDVAVGNDVAVVAGNDGNDVA200k8 pFVCMOEnable AC CouplingADC12D1800RFSNAS518I –JULY 2011–REVISED JANUARY 2014www.ti.comTable 2-1.

GNDVAGNDVAVAA GND-+100:100:VAAGNDVAAGND100VBIAS50k50kADC12D1800RFwww.ti.comSNAS518I –JULY 2011–REVISED JANUARY 2014Table 2-1. Analog Front-End and Clo

GNDVAGNDVAGNDVA50 k:VAGNDGNDVAADC12D1800RFSNAS518I –JULY 2011–REVISED JANUARY 2014www.ti.comTable 2-2. Control and Status Balls (continued)Ball No. Na

GNDVA100 k:GNDVA100 k:GNDVA50 k:GNDVAGNDVAADC12D1800RFwww.ti.comSNAS518I –JULY 2011–REVISED JANUARY 2014Table 2-2. Control and Status Balls (continued

VAGNDGNDVA100 k:ADC12D1800RFSNAS518I –JULY 2011–REVISED JANUARY 2014www.ti.comTable 2-2. Control and Status Balls (continued)Ball No. Name Equivalent

VDRDR GND+-+-VDRDR GND+-+-ADC12D1800RFwww.ti.comSNAS518I –JULY 2011–REVISED JANUARY 2014Table 2-3. Power and Ground Balls (continued)Ball No. Name Equ

VDRDR GND+-+-VDRDR GND+-+-ADC12D1800RFSNAS518I –JULY 2011–REVISED JANUARY 2014www.ti.comTable 2-4. High-Speed Digital Outputs (continued)Ball No. Name

ADC12D1800RFwww.ti.comSNAS518I –JULY 2011–REVISED JANUARY 2014These devices have limited built-in ESD protection. The leads should be shorted together

ADC12D1800RFwww.ti.comSNAS518I –JULY 2011–REVISED JANUARY 2014Contents1 Introduction ...

I / OGNDVATO INTERNALCIRCUITRYADC12D1800RFSNAS518I –JULY 2011–REVISED JANUARY 2014www.ti.comOperating Ratings(1)(2)(continued)VIN+/- Power 15.3 dBm (m

ADC12D1800RFwww.ti.comSNAS518I –JULY 2011–REVISED JANUARY 20143.5 Converter Electrical CharacteristicsDynamic Converter Characteristics(1)ADC12D1800RF

ADC12D1800RFSNAS518I –JULY 2011–REVISED JANUARY 2014www.ti.comConverter Electrical CharacteristicsDynamic Converter Characteristics(1)(continued)ADC12

ADC12D1800RFwww.ti.comSNAS518I –JULY 2011–REVISED JANUARY 2014Converter Electrical CharacteristicsDynamic Converter Characteristics(1)(continued)ADC12

CIN, DIFFCIN, PIN-TO-GNDCIN, PIN-TO-GNDVIN+VIN-ADC12D1800RFSNAS518I –JULY 2011–REVISED JANUARY 2014www.ti.com3.6 Converter Electrical CharacteristicsA

ADC12D1800RFwww.ti.comSNAS518I –JULY 2011–REVISED JANUARY 20143.7 Converter Electrical CharacteristicsI-Channel to Q-Channel CharacteristicsADC12D1800

ADC12D1800RFSNAS518I –JULY 2011–REVISED JANUARY 2014www.ti.com3.10 Converter Electrical CharacteristicsDigital Control and Output Pin CharacteristicsA

ADC12D1800RFwww.ti.comSNAS518I –JULY 2011–REVISED JANUARY 20143.11 Converter Electrical CharacteristicsPower Supply CharacteristicsADC12D1800RFUnitsSy

ADC12D1800RFSNAS518I –JULY 2011–REVISED JANUARY 2014www.ti.comConverter Electrical CharacteristicsAC Electrical Characteristics (continued)ADC12D1800R

ADC12D1800RFwww.ti.comSNAS518I –JULY 2011–REVISED JANUARY 20143.13 Converter Electrical CharacteristicsSerial Port InterfaceADC12D1800RFUnitsSymbol Pa

ADC12D1800RFwww.ti.comSNAS518I –JULY 2011–REVISED JANUARY 20146.2.2 Extended Control Mode ...

VD+VD-VOS GND½×VOD = | VD+ - VD- |½×VOD VD-VD+ADC12D1800RFSNAS518I –JULY 2011–REVISED JANUARY 2014www.ti.com4 Specification DefinitionsAPERTURE JITTER

ADC12D1800RFwww.ti.comSNAS518I –JULY 2011–REVISED JANUARY 2014LVDS OUTPUT OFFSET VOLTAGE (VOS) is the midpoint between the D+ and D- pins output volta

ACTUAL POSITIVEFULL-SCALETRANSITION-VIN/2ACTUAL NEGATIVEFULL-SCALE TRANSITION1111 1111 1111 (4095)1111 1111 1110 (4094)1111 1111 1101 (4093)MID-SCALET

tODtADSample NDQSample N+1DQSample N-1VINQ+/-CLK+DCLKQ+/-(0° Phase)DQ Sample N-35Sample N-36tOSKSample N-34 Sample N-33 Sample N-37tODtADSample NDISam

tODtADSample NDISample N+1DISample N-1VINQ+/-CLK+DCLKQ+/-(0° Phase)DQ, DI Sample N-35.5, N-35tOSKSample N-34.5, N-34 Sample N-33.5, N-33 Sample N-36.5

SCLK18 924Single Register AccessSCSSDICommand FieldMSBLSBData FieldtSSUtSHtSCStHCStHCSSDO read mode)MSBLSBData FieldtBSUHigh Z High ZCalRunPOWER SUPPL

-50 0 50 100678910ENOBTEMPERATURE (°C)NON-DES MODEDES MODE1.8 1.9 2.0 2.1 2.2678910ENOBVA(V)NON-DES MODEDES MODE0 4095-0.75-0.50-0.250.000.250.500.75D

1.8 1.9 2.0 2.1 2.2505254565860SNR (dB)VA(V)NON-DES MODEDES MODE0 600 1200 1800505254565860SNR (dB)CLOCK FREQUENCY (MHz)NON-DES MODEDES MODE0.75 1.00

0 1000 2000 3000-80-70-60-50-40THD (dBc)INPUT FREQUENCY (MHz)NON-DES MODEDES MODE-50 0 50 1004050607080SFDR (dBc)TEMPERATURE (°C)NON-DES MODEDES MODE1

0 600 1200 1800-100-75-50-250AMPLITUDE (dBFS)FREQUENCY (MHz)DESI MODE0 600 1200 1800-100-75-50-250AMPLITUDE (dBFS)FREQUENCY (MHz)0 1000 2000 300040506

ADC12D1800RFSNAS518I –JULY 2011–REVISED JANUARY 2014www.ti.com6.4.5.1 Power Planes ...

0 600 1200 18002.02.53.03.54.04.55.0POWER (W)CLOCK FREQUENCY (MHz)NON-DEMUX MODEDEMUX MODE0 1000 2000 3000-90-80-70-60-50-40-30CROSSTALK (dB)AGGRESSOR

ADC12D1800RFwww.ti.comSNAS518I –JULY 2011–REVISED JANUARY 20146 Functional DescriptionThe ADC12D1800RF is a versatile A/D converter with an innovative

ADC12D1800RFSNAS518I –JULY 2011–REVISED JANUARY 2014www.ti.comTable 6-1. Non-ECM Pin SummaryPin Name Logic-Low Logic-High FloatingDedicated Control Pi

ADC12D1800RFwww.ti.comSNAS518I –JULY 2011–REVISED JANUARY 20146.2.1.4 Calibration Pin (CAL)The Calibration (CAL) Pin may be used to execute an on-comm

ADC12D1800RFSNAS518I –JULY 2011–REVISED JANUARY 2014www.ti.comTo use this feature in ECM, use the Configuration Registers (Addr: 3h and Bh). See Input

SDISDOR/W1 0 A3 A2 A1 A0 XD14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0D1521 43 65 87 109 1211 1413 1615 1817 2019 2221 2423 25*Only required to b

SDISDOR/W1 0 A3 A2 A1 A0 X D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D021 43 65 87 109 1211 1413 1615 1817 2019 2221 2423 25SCLKSCSbADC12D180

ADC12D1800RFwww.ti.comSNAS518I –JULY 2011–REVISED JANUARY 2014Table 6-4. Features and Modes (continued)Control PinFeature Non-ECM ECM Default ECM Stat

ADC12D1800RFSNAS518I –JULY 2011–REVISED JANUARY 2014www.ti.com6.3.1.3 Input Offset AdjustThe input offset adjust for the ADC12D1800RF may be adjusted

DataDCLK 0° ModeDCLK 90° ModeADC12D1800RFwww.ti.comSNAS518I –JULY 2011–REVISED JANUARY 20146.3.1.6 Sampling Clock Phase (Aperture) Delay AdjustNOTESam

ADC12D1800RFwww.ti.comSNAS518I –JULY 2011–REVISED JANUARY 2014List of Figures2-1 ADC12D1800RF Non-DES Mode IMD3...

DataDCLK SDR RisingDCLK SDR FallingADC12D1800RFSNAS518I –JULY 2011–REVISED JANUARY 2014www.ti.comFor SDR, the DCLK frequency is the same as the data r

ADC12D1800RFwww.ti.comSNAS518I –JULY 2011–REVISED JANUARY 2014Table 6-5. Supported Demux, Data Rate ModesNon-Demux Mode 1:2 Demux ModeDDR 0° Mode only

ADC12D1800RFSNAS518I –JULY 2011–REVISED JANUARY 2014www.ti.comTable 6-7. Test Pattern by Output Port inNon-Demux Mode (continued)Time Q I ORQ ORI Comm

ADC12D1800RFwww.ti.comSNAS518I –JULY 2011–REVISED JANUARY 20146.3.3.3 Power-on CalibrationFor standard operation, power-on calibration begins after a

ADC12D1800RFSNAS518I –JULY 2011–REVISED JANUARY 2014www.ti.com6.3.3.6 Read / Write Calibration SettingsWhen the ADC performs a calibration, the calibr

ADC1XD1X00VINI+50: SourceVINI-1:1 BalunCcoupleCcouple100:VINQ+VINQ-100:CcoupleCcoupleADC12D1800RFwww.ti.comSNAS518I –JULY 2011–REVISED JANUARY 20146.4

ADC12D1800RFSNAS518I –JULY 2011–REVISED JANUARY 2014www.ti.comIn the case that only one channel is used in Non-DES Mode or that the ADC is driven in D

ADC12D1XXXVIN+50: SourceVIN-1:2 BalunCcoupleCcouple100:VIN+VIN-VCMOADC12D1XXXCcoupleCcoupleADC12D1800RFwww.ti.comSNAS518I –JULY 2011–REVISED JANUARY 2

CLK+CLK-ADC12D1XXXCcoupleCcoupleADC12D1800RFSNAS518I –JULY 2011–REVISED JANUARY 2014www.ti.com6.4.2 THE CLOCK INPUTSThe ADC12D1800RF has a differentia

ADC12D1800RFwww.ti.comSNAS518I –JULY 2011–REVISED JANUARY 20146.4.2.5 CLK JitterHigh speed, high performance ADCs such as the ADC12D1800RF require a v

ADC12D1800RFSNAS518I –JULY 2011–REVISED JANUARY 2014www.ti.comList of Tables2-1 Analog Front-End and Clock Balls ...

ADC12D1800RFSNAS518I –JULY 2011–REVISED JANUARY 2014www.ti.com6.4.3.3 Terminating Unused LVDS Output PinsIf the ADC is used in Non-Demux Mode, then on

CLKMaster ADC12D1XXXSlave 1 ADC12D1XXXSlave 2 ADC12D1XXXCLKCLKCLKRCLKRCLKRCOut1RCOut2DCLKDCLK DCLKRCLKRCOut1RCOut2RCOut1RCOut2ADC12D1800RFwww.ti.comSN

ADC12D1800RFSNAS518I –JULY 2011–REVISED JANUARY 2014www.ti.com6.4.5 SUPPLY / GROUNDING, LAYOUT AND THERMAL RECOMMENDATIONS6.4.5.1 Power PlanesAll supp

Cross Section LineIC DieNot to ScaleMold CompoundCopper Heat SlugSubstrate4JC_24JC_11.9V ADC MainSwitching RegulatorLinear RegulatorVDRVEVAVTCHV or Un

ADC12D1800RFSNAS518I –JULY 2011–REVISED JANUARY 2014www.ti.comThe center ground balls should be soldered down to the recommended ball pads (See AN-112

Power-on CalibrationOn-command CalibrationPower to ADCCalibrationCalDlyPull-up/down resistors set Control PinsADC output validADC12D1800RFwww.ti.comSN

FPGA writes Control PinsPower-on CalibrationOn-command CalibrationPower to ADCCalibrationCalDlyFPGA writes Control PinsPower-on CalibrationOn-command

VADCLK19001710timemV66063514905203001210Slope = 1.22V/msADC12D1800RFwww.ti.comSNAS518I –JULY 2011–REVISED JANUARY 2014Figure 6-15. Supply and DCLK Ram

LM95213100 pFADC12D1XXXIRIE = IF100 pF76D1+D2+5D-FPGAIRIE = IFADC12D1800RFSNAS518I –JULY 2011–REVISED JANUARY 2014www.ti.comIn the following typical a

ADC12D1800RFwww.ti.comSNAS518I –JULY 2011–REVISED JANUARY 20146.5 Register DefinitionsTwelve read / write registers provide several control and config

ADC12D1800RFwww.ti.comSNAS518I –JULY 2011–REVISED JANUARY 2014ADC12D1800RF 12-Bit, Single 3.6 GSPS RF Sampling ADCCheck for Samples: ADC12D1800RF1 Int

ADC12D1800RFSNAS518I –JULY 2011–REVISED JANUARY 2014www.ti.comBit 11 PDI: Power-down I-channel. When this bit is set to 0b, the I-channel is fully ope

ADC12D1800RFwww.ti.comSNAS518I –JULY 2011–REVISED JANUARY 2014Table 6-18. I-channel Full Scale Range AdjustAddr: 3h (0011b) POR state: 4000hBit 15 14

ADC12D1800RFSNAS518I –JULY 2011–REVISED JANUARY 2014www.ti.comTable 6-21. Bias AdjustAddr: 6h (0110b) POR state: 1C2EhBit 15 14 13 12 11 10 9 8 7 6 5

ADC12D1800RFwww.ti.comSNAS518I –JULY 2011–REVISED JANUARY 2014Table 6-26. Q-channel Full-Scale Range AdjustAddr: Bh (1011b) POR state: 4000hBit 15 14

ADC12D1800RFSNAS518I –JULY 2011–REVISED JANUARY 2014www.ti.comTable 6-28. Aperture Delay Fine Adjust(1)Addr: Dh (1101b) POR state: 0000hBit 15 14 13 1

ADC12D1800RFwww.ti.comSNAS518I –JULY 2011–REVISED JANUARY 2014Table 6-30. ReservedAddr: Fh (1111b) POR state: 001DhBit 15 14 13 12 11 10 9 8 7 6 5 4 3

ADC12D1800RFSNAS518I –JULY 2011–REVISED JANUARY 2014www.ti.comRevision HistoryNOTE: Page numbers for previous revisions may differ from page numbers i

PACKAGE OPTION ADDENDUMwww.ti.com7-Mar-2015Addendum-Page 1PACKAGING INFORMATIONOrderable Device Status(1)Package Type PackageDrawingPins PackageQtyEco

PACKAGE OPTION ADDENDUMwww.ti.com7-Mar-2015Addendum-Page 2In no event shall TI's liability arising out of such information exceed the total purch

MECHANICAL DATANXA0292Awww.ti.com

ADC12D1800RFSNAS518I –JULY 2011–REVISED JANUARY 2014www.ti.com2 Device Information2.1 Block Diagram8 Device Information Copyright © 2011–2014, Texas I

IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and otherch

905 910 915 920 925 930 935 940-120-90-60-300MAGNITUDE (dBFS)FREQUENCY (MHz)Fin = 2.7 GHz0 1 2 3 4-100-90-80-70-60-50-40IMD3(dBFS)INPUT FREQUENCY (GHz